Jerrin Joseph

About Jerrin Joseph

ASIC-SOC Design Engineer (Contractor )SanDisk India Device Design Pvt Ltd- Bangalore, India (February-2017 to present)Key Duties- Part of ASIC Development team- Working in designing Memory controllers for USB and SSD’s- Experience in CDC checks using meridian cdc- Experience in LINT - Experience in LEC checks using formality- Experience on UPF development, Multi-Voltage Rule Checks of SSD controller- Completed VLSI Front end Design and Verification training at Maven Silicon, Bangalore- Completed M.Tech from NIT Trichy in Process Control and Instrumentation- Actively seeking internships or Co-op / Full-Time opportunities in VLSI domainTechnical Skills:Design : RTL Design, Gate Level Design, Synthesis. Design Tools : Xilinx ISE, Ascent lint, meridian cdc, formality, conformal, ncverilog, simvisionHDLs : Verilog.HVLs: System Verilog Others : Adobe, Microsoft Word, Excel, PowerPoint- Interested in RTL Design, Digital Circuit Design, ASIC Design, SoC Design.

Experience

1. Senior Engineer

   Qualcomm

   Dec 2019 — Present · Bengaluru, IN

Education

• Rajagiri School of Engineering and Technology ,Kerala

  Engineer's Degree, Applied Electronics and Instrumentation

  2008 — 2012

• Ihrd

  Electronics

  2006

• National Institute of Technology, Tiruchirappalli

  Master's Degree, Process Control and Instrumentation

  2013 — 2015

Skills

• C++
• System Verilog
• Rtl Design
• System on a Chip (Soc)
• Riviera Pro
• Microsoft Excel
• Powerpoint
• Windows
• Field-Programmable Gate Arrays (Fpga)
• Microsoft Powerpoint
• Project Planning
• Instrumentation
• Troubleshooting
• Application-Specific Integrated Circuits (Asic)
• Xilinx Ise
• Uvm
• Verilog
• Matlab
• C
• Cdc
• Very-Large-Scale Integration (Vlsi)
• Simulink
• Systemverilog
• Engineering
• Commissioning
• Linux
• Microsoft Word
• Electronics
• Fpga Validation
• Perl Scripting