Jenith K

About Jenith K

Accomplished professional with 6 years of specialized experience in FPGA Design, featuring the following areas: Proficiency in FPGA prototyping, system-level integration, and verification using industry-standard tools: Vivado, ISE, and Quartus Prime. In-depth expertise in static timing analysis (STA) and CDC synchronizers, ensuring robust and reliable designs. Comprehensive understanding of HDL/HDVL, with adeptness in RTL Design Concepts using Verilog, VHDL, and System Verilog. Hands-on mastery and nuanced comprehension of key Protocols and IPs, including AXI3, AXI4, DDR4, I2C, SPI, UART, and Ethernet. Proven ability to develop self-checking testbench code, facilitating comprehensive verification. Possesses adept debugging skills for swift issue resolution. Additional Skills: Proficient in scripting languages such as Python, TCL, and Bash, bolstering automation capabilities. Hands-on experience with SVN and GitHub Version Control Tools, ensuring efficient collaboration and version management. More Attributes: Demonstrates excellent communication and problem-solving prowess. Adaptable to dynamic environments, thriving in challenging scenarios.Technology Enthusiast and Lifelong Learner

Experience

1. Engineer Ii - Fpga Design

   Microchip Technology Inc.

   Apr 2024 — Present · Hyderabad, IN

Education

• National Engineering College

  Bachelor of Engineering - BE, Electronics and Communication Engineering

  2016 — 2020

• Karapattai Nadar Higher Secondary School

  12th standard, Mathematical Biology

  2014 — 2016

• Karapattai Nadar Higher Secondary School

  10th Standard,

  2013 — 2014