Jen-Tai Hsu

Vice President of R & d @Silicon Motion

San Jose, CA, US
MOBILE NUMBERS
+19•••••••47

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WORK HISTORY

May 2024 — Present

Vice President of R & d @Silicon Motion

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Zhubei City, TW

In charge of R&D of Algorithm and Technology. Leading R&D teams to develop world leading SSD Controller with innovative Nand Controller Algorithms and Technology. Leading teams in internal key analog and Mixed Signal IP development for DDR, ONFI, PLL, LDO, UFS 4 and 5, MIPI M-PHY, PCIe PHY, SerDes PHY, etc. leading teams in Digital PHY development. Leadings teams in Physical Design in both custom layout as well as APR.5. Leading Analog CAD team.

EDUCATION

1983 — 1987

National Taiwan University

BS, Electrical Engineering

1990 — 1993

UCLA

Ph. D., Electrical Engineering

1988 — 1990

Case Western Reserve University

MS, Electrical Engineering

SKILLS

Very-Large-Scale Integration (Vlsi)Signal ProcessingDigital Signal ProcessorsAnalog Circuit DesignSystem on a Chip (Soc)SocField-Programmable Gate Arrays (Fpga)Power ManagementYieldPcieIcSemiconductorsSemiconductor IndustryApplication-Specific Integrated Circuits (Asic)Signal IntegritySramLow-Power DesignMixed SignalCircuit DesignElectronicsEmbedded SystemsEdaProduct EngineeringSiliconTclAnalogSystemverilogSerdesFpgaAsicPllIntegrated Circuit DesignVlsiEngineering ManagementCmosIntegrated Circuits (Ic)

ABOUT JEN-TAI HSU

Extensive executive and hands-on technical R&D experience in IOT, SoC, ASIC, IP, NVM, OTP, SerDes, and Analog Mixed Signal products. Provides one stop consultation for making your products working in minimum TTM consultation from various IP architecture and design, Third party IP selection advice and evaluation, SoC integration, Tape out, Package Design, Silicon Debug, Product Engineering, Test Engineering, Q&R, all the way to production.I have diversified industry experience with 2 years working in the FAB as process integration engineer and 2 years as product engineer in flash memory and over 20 years of Analog/Mixed Signal in product and SoC IP design and management experience. Hold 8 US patents with Intel and 6 patents with GUC and published more than a dozen papers in the field of circuit design and solid state device physics. Pioneered and founded high performing SerDes/memory/data converter IP team in SoC design service company. Key IP portfolio in production including 10G KR/XFI/EPON/GON, PCI-e Gen3, SATA 3.0/SAS 2.0, USB 3.0, DDR3/2/LPDDR2. Initiated 28G SerDes R&D for 100G Ethernet application, and an Uni-PHY covering multiple standards up including SAS 3.0 (12Gbps). IOT experiences on extremely low power IP and products developed in Pericom Corporation and Kilopass Technology, Inc.More than 30 patents issued or pending in US, Taiwan, and China. Areas in SerDes as well as memories and mixed signals, and analog.

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Jen-Tai Hsu — Email, Phone Number & Contact Info | Unifers