Jeff Pangborn
Working in Silicon Valley
- Role
- Engineer at Nokia
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jeff Pangborn
Expert in high-performance ASIC design using small geometry technologies. Proven experience with the entire ASIC design process, from system definition and micro-architecture design, through RTL coding and verification, to tape-out and silicon verification.Specialties: Verilog, SystemVerilog, Perl, C, Tcl, Unix/Linux, test equipment, Spyglass, VCS, DC, Verdi.
Experience
Engineer
Jun 2021 — Present · Sunnyvale, CA, US
Education
Carnegie Mellon University
BS
Santa Clara University
MS
Skills
- Perl
- Embedded Systems
- Semiconductors
- C
- System on a Chip (Soc)
- Debugging
- Soc
- Clearcase
- Pcie
- Systemverilog
- Microarchitecture
- Asic
- Application-Specific Integrated Circuits (Asic)
- Verilog
- Hardware
- Testing
- Tcl
- Functional Verification
- Rtl Coding
- Hardware Architecture
- Rtl Design
- Field-Programmable Gate Arrays (Fpga)
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