Jeff McNeal

About Jeff McNeal

Creative verification architect specializing in object oriented verification…

Experience

1. Asic & Fpga Verification Consultant

   Verilab

   Mar 2014 — Present

   Contracting with various clients around the world: Verification of audio processing DSP block. Worked with a team doing mixed signal & DSP UVM verification of an audio processing IP block. Performed requirements tracing back to product requirements document. Verification of FPGA based video processing block. Integrated a C reference model into a UVM/SV testbench, used UVM to generate frame data and checked that DUT response matches C prediction. Verification lead for a high speed, low latency networking system. The team designed and verified two FPGAs (NIC & SWITCH) for a proprietary networking protocol. Planned, architected and implemented UVM-like testbenches for both components. Lead team of three verification engineers working on both projects. Assisted software team with application and laboratory debug of the FPGAs. Verification team member working on verification of DDR based system using UVM/SystemVerilog testbench. Responsible for register verification using uvm_reg. Wrote scripts to generate UVM code from JSON register descriptions provided by client. Developed testbench infrastructure to verify reset and boot sequence.

Education

• Oregon State University

  BS CpE, Computer Engineering

  1991 — 1996

• Oregon State University

  MS CpE, Computer Engineering, Digital Signal Processing

  1996 — 1998