Jeff Marker
- Role
- Asic Design Engineer at Apple
- Location
- Ogden, UT, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jeff Marker
15 years of RTL/Verilog/VHDL design experience in FPGAs and ASICs 12 years of…
Experience
Asic Design Engineer
Jun 2020 — Present
Architecture of Low Power ML Inference Engine Front End ASIC Design
Skills
- Python
- Ieee 802.11
- Modelsim
- Rtl Design
- Ise
- Altera
- Wifi
- Powerpoint
- Wireless
- Verilog
- Matlab
- Field-Programmable Gate Arrays (Fpga)
- Digital Signal Processors
- Lte
- Vhdl
- Clearcase
- Fpga
- Xilinx
- Altera Quartus
- Ethernet
- Asic
- Embedded Systems
- Cvs
- Dsp
- Visio
- Perl
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