Jeevitha S
Senior Physical Design Engineer | 7× Silicon-Proven Tapeouts | RTL-to-GDS | Full-Chip Signoff | STA | EM/IR | SoC | Design Strategy & PPAC trade-off | Still learning, Still Improving 🚀
- Role
- Senior Project Engineer at Wipro
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jeevitha S
Learning in Physical Design:PD closure extends beyond timing, emphasizing effective Performance, Power, and Area (PPAC) trade-offs.Senior Physical Design Engineer with 7× successful silicon tapeouts and strong experience in RTL-to-GDS physical design and full-chip signoff. Skilled in STA, CTS, EM/IR, physical verification, and automation using TCL/Perl, with hands-on expertise in Fusion Compiler, ICC2, PrimeTime, Calibre, RedHawk, and Conformal.Experience working with external partners on Physical Design (PD) closure.Experience in Static Timing Analysis (STA) with an understanding of timing corners, margins, and derates.Hands-on experience with Synopsys and Cadence PnR tools.Experience with backend flows such as LEC, PI/SI, and DRC/LVS.Understanding of DFT methodologies, including Scan, MBIST, and LBIST.Understanding of Performance, Power, and Area (PPA) trade-offs.
Experience
Senior Project Engineer
Apr 2017 — Present · Bengaluru, IN
Education
School
ECE
SRV girls hr.sec.school
HIGHER SECONDARY, BIO-MATHS
2011 — 2013
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