Jeetpal Singh

About Jeetpal Singh

Experienced Professional in the area of Design for Test, including DFT Architecture planning, DFT Insertion, IP DFT test, Test Pattern generation and Verification, Silicon debug and failure analysis for leading technologies (16FF, 28nm 40nm, 65nm) and development of SOC Design Flow methodologiesKey focus Areas: DFT Architecture, Test Access, Memory test, ATPG, Transition fault test, Tetramax, Silicon debug, Technical lead, Mentor and build technical teams from fresh engineering graduates, interview & hiringExperience Summary : Expertise in SOC DFT Architecture planning which include, Test clock Architecture, Scan Compression and MBIST insertion for complex multi-million-gate SoC designs in leading technologies Experience in Interviewing, hiring and managing the DFT team Expertise in Automatic Test pattern generation for Stuck-At faults and Transition faults for PLL clock domains Experience in working closely with physical design teams for smooth timing closure of DFT logic. Experienced in deriving physical design friendly DFT architecture, Primary owner of DFT STA constraints Experience in Low power DFT, worked on different ways to reduce Test Power Experience in working closely with product engineering teams to perform Silicon debug & Shmoo analysis and ensured first pass silicon success SOCdesign methodology improvements to improve execution efficiency and reduce the test time for Multi-million gate ASIC’s. Expertise in debugging Zero-delay and SDF GLS Sound knowledge in Boundary Scan & Sound knowledge in P1500 Proficient in Perl, Shell and TCL Scripting

Experience

1. Sr Manager Silicon Design Engineering

   AMD

   Sep 2023 — Present · Bengaluru, IN

Education

• National Institute of Technology, Jalandhar

  B tech, Electronics and communication

  1998 — 2002

Skills

• Unix
• Debugging
• Asic
• Eda
• Rtl Design
• Verilog
• Physical Design
• Vlsi
• Functional Verification
• Soc
• Static Timing Analysis
• Rtl