Jeet Dewangan

About Jeet Dewangan

I\'m currently pursuing my Masters in Electronics and Communication Engineering (ECE) from the esteemed National Institute of Technology, Allahabad(MNNIT),while simultaneously training at VLSIFORALL training institute in RTL Design and Verification course, honing skills in cutting-edge verification methodologies. In this training I’m learning about Verilog, System Verilog, UVM, scripting with PERL, alongside project experience on various protocols like SPI,UART etc. My academic pursuits and training have equipped me with a robust skill set encompassing Verilog,System Verilog, Digital Electronics, Digital IC Design,Computer Architecture,UVM, MATLAB, Static Timing Analysis,ARM Processor and Cadence Virtuoso. I have a keen interest in VLSI, verification, validation, RTL design, VLSI Design flow, and Static Timing Analysis.Motivated by a passion for innovation and a drive to excel in the semiconductor industry, I am committed to leveraging my academic and practical experiences to make meaningful contributions to projects in VLSI design and verification.

Experience

1. Deg Design

   Micron Technology

   Sep 2024 — Present · Hyderabad, IN

Education

• Motilal Nehru National Institute Of Technology

  Master's degree

  2022 — 2024

• Bhilai Institute of Technology (BIT), Durg

  Bachelor's degree

  2017 — 2021