Jebaseelan Varuvel

About Jebaseelan Varuvel

19+ years of technical innovations and management experience in semiconductor chip physical design implementation including GPU, CPU and SoC- High performance, low power, multi-million gates, lower nodes (up to 3nm) chip tape-outs using Synopsys and Cadence tools- High competence in roles from techno-management with project/team handling to Individual contributor - Alumnus of the prestigious Birla Institute of Technology and Science, Pilani.Professional Competencies- Rich experience in multimillion gates, high performance Networking and Graphics SoCs tapeouts- Relevant experience in complete physical design implementation of cutting edge deep submicron technology nodes using Synopsys and Cadence EDA tools- Core expertise in physical design place and route implementation flows, Timing Closure, Physical Verification, Electro-migration and IR drop analysis, ECO implementation- TCL/AWK/Shell/Python scripting for reports extraction and tool data model access and flow automation- Interacting with Frontend team and Fullchip team for Netlist quality and floorplan, timing and physical verification for fullchip closure.EDA Tools:PNR: Synopsys’ ICC2, Cadence InnovusExtraction and Timing sign-off: Synopsys StarRC, PrimeTime, PrimeTime-SIPhysical Verification: Synopsys’ IC Validator, Mentor\'s CalibrePeople Skills- Successfully contributed in tapeouts managing a large team of engineers globally across different time zones (Mostly across USA and India)- Built up teams from scratch up, enabled them to deliver and receive accolades from internal as well as client team- Have worked as an onsite engineer in USA as well as India offshore team management- Comfortably worked in various capacity of roles like Individual Contributor, Team Lead, People management etcOrganizational Skills- Hiring, training, performance evaluation, career roadmap- Contributing to build campus relationship, participating to build industry academia relationshipMy key value add is to go above and beyond the daily assigned work activities. Key areas of critical contributions revolves around management, mentoring, employee engagement, and talent acquisition for the GPU-PD business unit. The staggering number of awards clinched in a short span of time exemplifies that unique mettle to rise and perform exceptionally beyond daily assigned tasks.

Experience

1. Senior Staff Engineer

   美商高通國際股份有限公司

   May 2024 — Present · Austin, TX, US

Education

• Birla Institute of Technology and Science, Pilani

  Master of Science - MS, Microelectronics

  2007 — 2011

• The University of Texas at Austin

  Post Graduate Program in Artificial Intelligence and Machine Learning