Jean Min
RISC-V CPU/SOC Microarchitecture/RTL Lead
- Role
- Soc Cpu Rtl Design Engineer at Intel
- Location
- Palo Alto, CA, US
- LinkedIn followers
- 500 followers
About Jean Min
Experienced Design Engineer with a demonstrated history of working in the semiconductors industry. Strong engineering professional skilled in Semiconductors, Debugging, Functional Verification, Verilog, and Integrated Circuits (IC).
Experience
Soc Cpu Rtl Design Engineer
Nov 1995 — Present · Santa Clara, CA, US
Education
National Taiwan University
Bachelor of Science - BS, ee
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