Jean-Marie Taupin
Vérification Engineer @Scalinx
Grenoble, FR
EMAILS
MOBILE NUMBERS
+91 *********19
Signup · Get unlimited contacts
WORK HISTORY
Apr 2023 — Present
Vérification Engineer @Scalinx
View department →
EDUCATION
2012 — 2012
Cadence
UVM and System Verilog Verification.
2015 — 2015
SYNOPSYS
DFT Automatic Test Generation (ATPG)
1987 — 1988
Ecole du Pétrole et des Moteurs
Master's degree, Internal Combustion Engines
1983 — 1986
CentraleSupélec
Master's degree, Physical Sciences and Engineering.
1994 — 1994
CentraleSupélec
Digital Control Systems and Signal Processing.
2002 — 2002
University of California, Berkeley
Analog Design, Mixed Design, Cmos Device, C, Perl, Digital Design
2009 — 2009
ARM
Cortex A9 HW
SKILLS
PhySocVerilogSystems EngineeringAsicInternal Combustion EnginesIntegrated Circuit DesignInterconnectsSemiconductorsIcMixed-Signal Ic DesignAutomotiveDebuggingWirelessEmbedded Systems
ABOUT JEAN-MARIE TAUPIN
Currently unavailable anymore, I signed for a permanent position at Scalinx. I am…
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.