Jigar Vaidya
Staff Design Verification Engineer @高通
Mississauga, ON, CA
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jul 2024 — Present
Staff Design Verification Engineer @高通
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Toronto, ON, CA
EDUCATION
2016 — 2018
Concordia University
Master’s Degree, Electrical and Computer Engineering
ABOUT JIGAR VAIDYA
Design verification engineer with skills of | Design Verification (UVM|VMM)| Verilog testbenchLanguage - SystemVerilog, Verilog, VHDL, Perl, Bash, Python.Tools - VCS (Synopsys), Verdi, NC Verilog (Cadence), Mentor graphics, Discovery Visual Environment(DVE), Simvision, Perforce(P4), VSO.ai, Clearcase
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