John Cloudman

About John Cloudman

I have over 20 years of experience in leading and growing high performance silicon and platform design teams across the globe. I am self-motivated and driven to lead continuous improvement. I create and drive strategies across organizations and have led multiple server programs from concept to launch.

Experience

1. VP Gm, Hard Ip and Test Chip Development, Central Engineering

   Intel

   Nov 2025 — Present · Fort Collins, CO, US

   Leading global IP team that delivers all Analog/Hard IP for all Intel products and external customers• Key IPs include Memory IO, High Speed Serial IO, Die to Die/UCIe IO, Sensors, Power delivery, Security, and Clocking IP. Responsible for the entire lifecycle of execution from pathfinding to architecture to design to test chips to post silicon and customer support.• Responsible for organization vision, strategy and execution.

Education

• Rice University

  Bachelor of Science, Electrical and Computer Engineering

  1995 — 1999

Skills

• Application-Specific Integrated Circuits (Asic)
• Physical Design
• Very-Large-Scale Integration (Vlsi)
• Vlsi
• Semiconductors
• Electrical Engineering
• Hardware Architecture
• System on a Chip (Soc)
• Logic Design
• Eda
• Asic
• Debugging
• Computer Architecture
• Microprocessors
• Intel
• Processors
• Mixed Signal
• Circuit Design
• Soc