Jay Potnis

About Jay Potnis

Actively looking for full time positions in the field of VLSI Synthesis and Physical Design, VLSI Design Implementation and Design Automation. Willing to relocate- SoC Design Engineer with experience in developing Synthesis, Placement, Routing and Optimization methodologies for designs and automating these methods to be reused for multiple designs across multiple technology nodes- Experience working on Design Automation across multiple steps in the RTL to GDS flow. Working knowledge of multiple EDA tools such as Fusion Compiler, ICC2, Star RC extraction, Prime Time- Possess basic working knowledge of whole ASIC design flow consisting of synthesis, automatic place and route, design optimization, extraction, timing closure, formal equivalence verifications, reliability verification- Experience creating automated scripts for reporting and comparing design QoR.My areas of interest are VLSI Synthesis & Physical Design and Design Automation. Along with VLSI design fundamentals, I also have a strong command over scripting languages Python, TCL, Perl, Unix, C and C++. Knowledge of writing design description in Verilog/System Verilog at multiple abstraction levels.I also have an experience working on deep learning frameworks like PyTorch, TensorFlow and Keras through my Graduate Research Assistantship and Thesis on \"DEEP NEURAL NETWORK BASED RAIN/NO-RAIN CLASSIFICATION AND RAIN RATEESTIMATION\" at Colorado State University.

Experience

1. Physical Design Methodology Engnieer

   Intel

   Oct 2023 — Present · Hillsboro, OR, US

Education

• Colorado State University

  Master of Science - MS, Electrical and Computer Engineering

• Ramrao Adik Institute of Technology

  Bachelor of Engineering, Electrical and Electronics Engineering

  2015 — 2019