Jay Patel
Rtl to gds methodology and PPA improvement.
- Role
- Principal Member of Technical Staff at AMD
- Location
- Sunnyvale, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jay Patel
Leading team to develop RTL to GDS Physical design methodologies on bleeding edge technologies and PPA (Power, Performance, Area ) targets.
Experience
Principal Member of Technical Staff
Jul 2023 — Present · Santa Clara, CA, US
Education
South Gujarat University
BE, Electronics and communication
2000 — 2004
DA-IICT
M. Tech, VLSI
2004 — 2006
SCET
B. E., Electronics and Communication
2000 — 2004
Skills
- Timing Closure
- Logic Design
- Tcl
- Vlsi
- Primetime
- Cadence
- Ic
- Semiconductors
- Physical Design
- Perl
- Eda
- Static Timing Analysis
- Drc
- Scripting
- Magma
- Asic
- Soc
- Debugging
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