Jaypal Rathod
CXL, DDR Protocol specific IP Verification Engineer @Synopsys || Ex- Intel || M.Tech @NIT Karnataka || VJTI
- Role
- Senior Verification Engineer at Synopsys Inc
- Location
- Mumbai, IN
- LinkedIn followers
- 500 followers
About Jaypal Rathod
Presently working as Senior Verification engineer for CXL, PCIE, DDR, UDIMM, RDIMM, DFI…
Experience
Senior Verification Engineer
Jun 2023 — Present · Hyderabad, IN
Working in IP Verification Team (VIP) which focuses on the development, Integration & providing solutions related to VIP’s & Test Suite. Verification Engineer for PCIe and CXL,DDR, UDIMM, RDIMM, DFI protocol specific Designs.1. Daily regression analysis for CXL using simulation and emulator tools.2.Debugging the failed testcases and finding root cause of failure testcase.3. knowledge of PCIE Gen1/Gen2/Gen3/Gen4/Gen5/ Gen6 protocols.4. Working on High speed interconnect CXL1.0/CXL1.1/CXL2.0/CXL3.0 IP Level verification.5. Creating testcases and bring up those features into regression.6. Finding bugs and improve quality of IP as per the specifications.7. Knowledge on cache Coherence protocol(MESI states) and CXL.mem.8. Knowledge of DDR, UDIMM, RDIMM Spec with VIP working experience.
Education
Dayanand Science College, Latur
High School/Secondary Diplomas and Certificates
2013 — 2015
National Institute of Technology Karnataka
Master of Technology - MTech
2021 — 2023
Veermata Jijabai Technological Institute (VJTI)
B.Tech
2015 — 2019
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