Jaymin Patel

About Jaymin Patel

A San Jose State Graduate specialized in ASIC/SoC/ FPGA Design and Validation working as a Product Development Engineer at Intel Corporation.Programming SkillsVerilog HDL, System Verilog, Scripting (Python, Perl, TCL), C, C++ Digital ElectronicsDigital Logic Design, Static Timing Analysis (STA), Timing/Area/Power Optimization, Low power techniques, Place and Route, DFT- Design For Test (Scan Insertion,ATPG and BIST).Bus ProtocolsNon-Volatile Memory Express (NVME), PCIE (TLP), AXI, AHB, APB, I2C, I3C, SPIUSB/PCIe protocol Computer ArchitectureMIPS Architecture, Cache Organization, Parallelism, Virtual Memory, Memory Controller, Virtual MemoryEDA ToolsSynopsys VCS, Cadence NCSim, Design Compiler, Design Vision, Cadence NCVerilog, Virtuoso, GTK Wave, ModelSim, primetime, Multisim, Design Vision, Cadence Encounter, Cadence Virtuoso

Experience

1. Product Development Engineer

   Intel

   Dec 2020 — Present · Austin, TX, US

   Responsible for testability and manufacturability of integrated circuits from the component feasibility stage through production ramp.• Make significant contributions to design, development, and validation of testability circuits.

Education

• Gujarat Technological University (GTU)

  Bachelors of engineering, Electronics and communication engineering.

  2013 — 2016

• Gujarat Technological University (GTU)

  Associate's degree, Electronics and communication engineering

  2010 — 2013

• San José State University

  Master of Science - MS , Electrical engineering.

  2018 — 2020

• Kansas State University

  Bachelor's degree, Wireless Communication ,Digital Signal Processing

  2015 — 2015