Jaymeen Aseem
Memory Design Lead at Intel, India | Ex-TSMC | IIT Delhi
- Role
- Memory Design Lead at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jaymeen Aseem
10 years of industry experience in memory circuit design and verification and memory compiler development. Worked on different kinds of memories like SRAM/RF/ROM with various design aspects like single port, two port, high density, low leakage, multi bank, double pumped, etc. Seeking opportunities to work in leading memory products with best PPA targets.
Experience
Memory Design Lead
Feb 2022 — Present · Bengaluru, IN
Leading ROM compiler development and Ultra high density SRAM compiler development in latest technology nodes.
Education
GHSEB main
Higher secondary, Engineering
2007 — 2009
Nirma university
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2009 — 2013
Indian Institute of Technology, Delhi
Master of Technology (M.Tech.), Integrated Electronics and Circuits
2013 — 2015
Maniprabhu Highschool
S.S.C., Maths, Science and Social Studies
2006 — 2007
GHSEB-GUJCET
GUJCET, Science
2007 — 2009
Skills
- Encounter
- C
- Programming
- C++
- Vhdl
- Multisim
- Matlab
- Html
- Cadence Virtuoso
- Microsoft Office
- Vlsi
- Java
- Cadence Spectre
- Embedded Systems
- Synopsys Tools
- Lindo
- Microcontrollers
- Circuit Design
- Lingo
- Linux
- Ni Multisim
- Cadence Icfb
- Verilog
- Vlsi Design
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.