Jaykishan Dudhrejiya
ASIC Digital Design, Sr Engineer | Synopsys Inc
- Role
- Senior Design Verification Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jaykishan Dudhrejiya
I have 2+ years of experience in PCIe-CXL VIP development & verification along with a demonstarted history of working in the different Industry levels protocols, tools and technology. I am Self-motivated and committed entry-level engineer, with good grasping skills, looking for a challenging career which demands the best of my professional abilities in terms of technical and analytical skills and that helps me broaden and enhance my skillset and knowledge.Skills -1) HVL Language - SystemVerilog amd Verilog2) Verification Methodology - UVM3) Constraints Random Verification4) System Verilog Coverage - SVG5) Scripting Language - Shell and PerlExperience in Industry Protocols1) PCI Express 5.02) CXL 2.03) CAN Bus4) AXI5) AHB2APB Bridge
Experience
Senior Design Verification Engineer
Feb 2024 — Present · Bengaluru, IN
Education
Gujarat Technological University (GTU)
Bachelor of Engineering - BE
2016 — 2020
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