Jayesh Karwarker

About Jayesh Karwarker

9+ years of experience in top Semiconductor Companies with expertise in Low Power Design focusing on both Frontend and Backend aspect of design cycle. Understanding of latest technology nodes with project exposure to 7nm, 5nm and 3nm based designs.Profile Brief: Power Estimation using Synopsys PTPX, Cadence Joules Power optimization using Ansys Power Artist Low Power Methodology with UPF standard A skilled VLSI Engineer having expertise in FPGA/ASIC/VLSI design flow, functional simulation, synthesis, static timing analysis. Strong understanding of FPGA architecture. Skilled in VHDL, Verilog, System Verilog and C fundamentals. FPGA Architecture and design tools: Kintex, Xilinx Vivado Simulation tools: ModelSim, MATLAB. Verdi Scripts: TCL Basic understanding of PCIe protocol.

Experience

1. Graphics Power and Performance Engineer

   Intel

   May 2022 — Present · Bengaluru, IN

Education

• CDAC-ATC, Mumbai

  PG-Diploma, VLSI Design

• Goa Engineering College - Government of Goa

  Master of Engineering (M.E), Microelectronics

Skills

• Xilinx
• Microcontrollers
• Analog
• Cmos
• C++
• Semiconductors
• Electronics
• Ic
• Microprocessors
• Analog Circuit Design
• Modelsim
• Vhdl
• Verilog
• Vlsi
• C
• Spectre
• Matlab
• Cadence Virtuoso
• Soc
• Fpga
• Asic
• Html
• Mixed Signal