Jayesh Tanwani
Engineering Manager at Intel Corporation and Vice Chair IEEE CAS Member Activity
- Role
- Soc Design Engineering Manager at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jayesh Tanwani
I am a VLSI professional with over 13 years of experience driving innovation across the…
Experience
Soc Design Engineering Manager
Apr 2022 — Present · IN
Education
Cambridge Institute Of technology
Bachelor of Engineering (B.E.)
2008 — 2012
S.V.K.T College
12th; H.S.C
2006 — 2008
I.C.S.E Barnes School
10th
1995 — 2006
Skills
- Electronics
- Microsoft Word
- Event Planning
- Microsoft Office
- Vlsi
- Analysis
- Embedded Systems
- Linux
- Microsoft Excel
- Powerpoint
- Vhdl
- Windows
- Field-Programmable Gate Arrays (Fpga)
- Verilog
- Testing
- Xilinx
- C
- Programming
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.