Jayesh Ranjan Majhi
Senior Principal Design Engineer at Cadence Design Systems
- Role
- Senior Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jayesh Ranjan Majhi
Experienced ASIC Verification Engineer with a demonstrated history of working in the semiconductors industry 9+ years.* Certificated SemiConductor Automotive Functional Safety Professional from SGS-TÜV Saar GmbH* Proficiency in PCIe 6.0 protocol, UVM, System-Verilog, Verilog, and Scripting.* Hand-on on tools like vManger, vPlanner, Simvision and Xcelium* Operational experience in Cadence PCIe VIP* Strong engineering professional with a Bachelor’s Degree focused in Electrical and Electronics Engineering.
Experience
Senior Principal Design Engineer
Jan 2026 — Present · Bengaluru, IN
Education
NIST University
Bachelor’s Degree, Electrical and Electronics Engineering
2011 — 2015
Skills
- Simulink
- Microcontrollers
- System Verification
- Windows
- Shell Scripting
- Pcie
- Perl
- Digital Electronics
- Can Bus
- C
- Programming
- Uvm
- C++
- Power Electronics
- Electronics
- Vcs
- Verilog
- Pspice
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