Jayesh Pandey
Senior Methodology Engineer (Dft) @NVIDIA
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WORK HISTORY
Senior Methodology Engineer (Dft) @NVIDIA
San Francisco, CA, US
DFT Architect | In-System Test Innovator | DFT LeadArchitected MATHS (Mechanism to Access Test Data over High-Speed Link) using PCIe for structural testing at wafer and system levels.Deployed In-System Test (IST) solutions for memory and logic validation in the field, ensuring chip security for NVIDIA and customers.Led deployment & debug of in-system test solutions at customer sites, enhancing product reliability.Leading a team of 4-7 engineers, driving DFT strategy, risk assessment, and cross-functional collaboration.Designed key IP for In-system test covering scan, MBIST. Ensured hardware-software co-design and seamless integration of DFT solutions.
EDUCATION
ABV-Indian Institute of Information Technology and Management
M.Tech.
NIT Hamirpur (H.P.)
B.Tech.
ABOUT JAYESH PANDEY
Dynamic and results-oriented professional with over 18 years of DFT/DFX methodology…
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