Jayesh Kelur

Layout Design Engineer at Intel

Role
Layout Design Engineer at Intel
Location
Bengaluru, IN
LinkedIn followers
500 followers

About Jayesh Kelur

Analog/IO Layout design engineer with 7+ years of experience on technology nodes 10nm…

Experience

  1. Layout Design Engineer

    Intel

    Feb 2024 — Present · Bengaluru, IN

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Jayesh Kelur — Layout Design Engineer at Intel in Bengaluru, IN | Unifers