Jayendra Patel
Static Timing Analysis Engineer at Google
- Role
- Static Timing Analysis Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jayendra Patel
Have Experience in the field of STA, Physical Design and Memory QA Tool Development. Knowledge of STA Signoff Methodology and have done multiple tap-outs. Knowledge of complete PD Flow and involved in multiple tap-outs. Knowledge of Synthesis, CLP and LEC. Knowledge of Full Chip DFT architecture. Expertise in scripting languages like PERL, TCL and Linux/Shell. Strong experience in QA tool development for validation of IP collaterals (lib, lef, gds, spice, rtl, upf etc) generated through Memory Compiler (RF, ROM and SRAM). Proficient in Verilog, System Verilog and UVM Coding. Excellent troubleshooting and debugging skills.
Experience
Static Timing Analysis Engineer
Sep 2023 — Present · Bengaluru, IN
Education
Sardar Patel Vidyalaya
HSC, Science Stream
2005 — 2007
Gujarat University
BE(EC), Electrical, Electronics and Communications Engineering
2007 — 2011
DA-IICT
Master of Technology (M.Tech.), VLSI and Embedded Systems
2012 — 2014
Skills
- Fpga
- Asic
- Java
- System C
- Tcl
- Uvm
- Microcontrollers
- Unix Shell Script
- Very-Large-Scale Integration (Vlsi)
- Cadence Encounter
- Embedded C
- Perl
- Embedded Systems
- Functional Verification
- Cadence Virtuoso
- Vhdl
- C
- Assertion Based Verification
- Verilog
- Vlsi
- C++
- Systemverilog
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.