Jaydeep Rangani

About Jaydeep Rangani

Complete designing of dynamic logic memories, using latest techniques including domino logic-Designed Read logic of ROMs to meet design constraints at advanced technology node-Designed Write and Read logic of RF to meet design constraints at advanced technology node-Designed Write assist logic for RF(1R1W) to meet better write margin- Achieving best possible PPA (power, performance, area) by different memory architectures and circuit design- Good understanding of RF/ROM architecture, Critical Path Modelling, Marginality Analysis, optimization and Most Probable Point(MPP) method- Design/characterization of various types of Memory compilers, which include ROM, Multiport Register Files (RF) across various process technologies- Hands on experience in Formal Equivalence Verification (FEV) of RFs/ROMs- Good understanding of the bit-cell operation and different assist techniques required at advanced nodes- Low-Power High-Performance Transistor level circuit Design- Design & Analysis of various Memory/RF block.

Experience

1. Memory Design Engineer at Intel

   Intel

   Aug 2018 — Present · Bengaluru, IN

Education

• Sardar Patel Vidhyamandir, Rajkot.

  Associate's Degree, Mathematics

  2005 — 2007

• Govt engineering college rajkot

  Bachelor of Engineering (B.E.), Electrical and Electronics Engineering

  2007 — 2011

• Sardar Patel Vidhya mandir, Rajkot india.

  High School, Science

  2004 — 2005

• Daiict

  Master of Technology (M.Tech.), VLSI and Embedded System

  2012 — 2014

Skills

• Verilog
• Pspice
• Shell Scripting
• Vhdl
• Simulations
• Scripting
• Very-Large-Scale Integration (Vlsi)
• Memory Design
• Microprocessors
• Cadence
• Matlab
• Field-Programmable Gate Arrays (Fpga)
• Analog Circuit Design
• Fpga
• Xilinx Ise
• Physical Design
• Asic
• Systemverilog
• Rtl Design
• Electronics
• Microsoft Office
• Vlsi
• C
• Cadence Virtuoso
• Circuit Design
• C++
• Cmos
• Linux
• Modelsim
• Perl
• Semiconductors
• Digital Electronics