Jaydeep Muley
RTL Design Engineer at Wipro
- Role
- Rtl Engineer at Wipro
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jaydeep Muley
RTL Design Engineer with 6 plus years of experience, seeking job opportunity in VLSI domain and secure a challenging position where I can effectively contribute and enhance my skills.Currently working in RTL Design Domain for Premium-tier mobile SoC at Qualcomm Bangalore. My field of work involves Design of Control and Status Registers required by the cores across SoCPrior to this worked for Intel Client for MIPI and other SERDES IP development projects, where I worked on static checks like CDC and Lint and power checks for different IP\'s.Technical Skills:• Verilog, SystemVerilog.• Spyglass CDC, Questa CDC.• Spyglass Lint• VCS.• Scripting languages: PERL, Tcl.• Basics of STA.
Experience
Rtl Engineer
Jul 2020 — Present · IN
Education
Remote Customer Service Jobs
Master of Technology (MTech), VLSI Design
2015 — 2017
Skills
- Cadence Virtuoso
- Ncsim
- Cadence Encounter
- Drc
- Lvs
- Verilog
- Perl
- Tcl
- Rtl Design
- Rtl Verification
- C
- Fpga
- Asic
- Mentor Graphics
- Simulink
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.