Jayati Vyas
Senior Design Verification Engineer at Wipro Limited
- Role
- Senior Design Verification Engineer at Wipro
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jayati Vyas
7 years of experience as Design Verification Engineer working for top silicon clients.Demonstrated history of B.Tech (E&I) and M.Tech (VLSI) with Industrial training experience from BARC, Govt of India Current Organization: Wipro Past key Projects: Google (7 Months) Intel (13 Months) and Qualcomm (18 Months)COMPETENCIES Languages: Verilog, System Verilog, VHDL Coding Methodologies: UVM Tools: Simvision, Novas
Experience
Senior Design Verification Engineer
Nov 2020 — Present · Bengaluru, IN
Education
Banasthali Vidyapith
Master of Technology - MTech, VLSI Design
2014 — 2016
Shri Vaishnav Institute of Technology and Science, Indore
Bachelor of Technology - BTech, Electronics and Instrumentation
2009 — 2013
Skills
- Xilinx Ise,Cadence Virtuso,Silvaco,Verilog, System Verilog
- Vhdl Programming, Ms Office, Ms Dos, Window Xp and Internet Applications
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