Jayasekhar Tholiyil
Senior SoC micro Arch - Design Engineer at Intel Corporation
- Role
- Senior Soc Arch, Micro Arch & Design Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Jayasekhar Tholiyil
Highly regarded technical leader and SoC Microarchitecture - Design expert with a track…
Experience
Senior Soc Arch, Micro Arch & Design Engineer
Jan 2002 — Present
Versatile SoC Architecture, Micro-Architecture, Design, Debug and end to end ownership.* SoC Architecture of fabrics across various bus protocols, CPU subsystems, and SoC peripherals.* Micro-Architecture, Configurable RTL Development and ownership of the Design from concept through production.* Design development includes ARM-based SoC and fabrics, PCI-based interconnect fabric and End Points* Management units for Server chipsets, BIST engine for PCIe.* Owned Design development from concept through production.* SD support, Timing closure, various pre tape-in quality reviews.* Technical leadership demonstrated through debug expertise, fabric content expertise and mentorship.
Education
University of Calicut
Bachelor of Technology (B.Tech.)
Skills
- Asic
- Soc Architecture
- Vlsi
- Performance Bus Architecture
- Performance Bus Architecture
- C
- Embedded Systems
- Systemverilog
- Verilog
- Debugging
- Semiconductors
- Soc Design Process
- Interconnet Fabric
- Soc
- Ic
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