Jayapriya Ramesh
Physical Design and Verification Engineer at HCL Technologies
- Role
- Vlsi Design Engineer at HCLTech
- Location
- Chengalpattu, TN, IN
- LinkedIn followers
- 500 followers
Experience
Vlsi Design Engineer
Jul 2019 — Present · Bangalore, IN
Good knowledge in PNR flow, from RTL to GDSII in IC compiler and Fusioncompiler (Floor Planning, Power Planning, Placement, and Congestion Analysis, Clock TreeSynthesis, Detail Routing, Timing analysis and Physical verification).• Expertise in usage of Synopsys & Candance tools [ ICC, FC, INNOVUS, FLOW - Intel RDTand Lynx Flows].• Excellent understanding and hands on experience with physical verification(DRC/LVS/ERC/antenna) and other reliability checks (IR/EM/Xtalk)• Expertise in scripting using TCL
Education
SSN College of Engineering
Master of Engineering
2017 — 2019
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