Jayanth Kambhampati
| DV Intern at STM | Ex- RTL Design Intern at AMD | Actively looking for Full time opportunities in Design Verification and Validation roles.
- Role
- Design Verification Intern at STMicroelectronics
- Location
- Dallas-Fort Worth, TX, US
- LinkedIn followers
- 500 followers
About Jayanth Kambhampati
I\'m an Electrical and Computer Engineering Graduate student at Portland State University. I am currently interning as a Design Verification Intern at STM | Ex - RTL Design intern at AMD. I am actively looking for Full time opportunities in Design Verification Validation and Architecture roles Email ID : j•••••••@pdx.edu
Experience
Design Verification Intern
May 2023 — Present · Dallas, TX, US
Education
Portland State University
Master of Science - MS, Electrical and Computer Engineering, 4.0/4.0
2022
JNTUH College of Engineering Hyderabad
Bachelor's degree, Electrical, Electronics and Communications Engineering, 9.92/10
2016 — 2020
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