Jayanth Ramani
Sr Principal Application Engineer at Cadence Design Systems
- Role
- Sr Principal Applications Engineer at Cadence
- Location
- Beaverton, OR, US
- LinkedIn followers
- 500 followers
About Jayanth Ramani
Over 15 years of physical design experience in RTL/Netlist to GDSII flow • Possess excellent knowledge and experience of Magma, Synopsis, Mentor Graphics and Cadence tool suites.• Floorplan, Place and Route, Static Timing Analysis and Physical verification expertise. • Tapeout experience with 5nm, 14nm, 40nm, 65nm, 90nm and 130 nm designs.
Experience
Sr Principal Applications Engineer
Jul 2023 — Present
Education
Ohio University
MS, EE
2005 — 2007
Don Bosco Matriculation
High School
1998 — 2001
Anna University Chennai
B.E, Electrical and Electronics Engineering
2001 — 2005
Skills
- Eda
- Timing Closure
- Floorplanning
- Soc
- Logic Synthesis
- Drc
- Clock Tree Synthesis
- Power Analysis
- Cadence
- Vlsi
- Physical Design
- Physical Verification
- Magma
- Asic
- Static Timing Analysis
- Primetime
- Tcl
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