Jayanta Lahiri

About Jayanta Lahiri

OBJECTIVE• To make a significant impact to a Semiconductor Company, by driving excellence in Engineering through efficiency, quality and innovation. • To help grow the business by venturing into new domains and leverage my knowledge on Foundation IP design for various strategic decisions like, semiconductor process technology, design cycle time and cost.• Strategize, Plan and Execute.SKILLS PROFILE:ORGANIZATION• Played the leadership role in building engineering organization; helped bringing up two big design centers in India (Bangalore & Noida).• Ability to act as a strong bridge with Licensing, Marketing & Sales with relevant Engineering input to close contracts.• Ability to lead big Engineering Organization across geographic locations (San Jose, Austin, Grenoble, Bangalore, Noida).• Engage well with partners, vendors and customers; Ability to negotiate to attain win-win results and thus build strong, long lasting business relationships. o Responsible for driving EDA new tools deployment in Physical Design Group in ARM. Engineering resource capacity planning for the whole ARM-Physical Design Group, including contractors (total of 400), in terms of projects and scheduling. TECHNICAL• Excellent in-depth knowledge in Foundation IP, which includes memory compilers, logic libraries (Standard cell), GPIO, POP (Arm Core benchmarking) & silicon validation. • Silicon savvy - have participated & debugged in silicon issues at the Test chip level, understanding yield issues, design margins.• Well versed with both high performance IPs on FINFET processes needed for Enterprise as well as low power low cost IPs needed for IOT like 40nm processes. PEOPLE-Very good team player, can excite the team to reach much higher standards. Scored >4 (out of max 5) in a 180 degrees feedback-Absolutely passionate and self-driven. Taken multiple initiatives with excellent results around training, building new teams.

Experience

1. Vice President Technical Marketing

   M31 Technology

   Mar 2023 — Present · CA, US

   Help in Customer adoption of IP and have best in class PPA with the highest quality level

Education

• Indian Institute of Engineering Science and Technology (IIEST), Shibpur

  Bachelor of Engineering (B.E.), Electrical Engineering

  1982 — 1986

• Indian Institute of Technology, Madras

  M.Tech, Microelectronics

  1986 — 1988

Skills

• Ic
• Low-Power Design
• Fpga
• Asic
• Semiconductor Industry
• Vlsi
• Static Timing Analysis
• Soc
• System on a Chip (Soc)
• Debugging
• Semiconductors
• Verilog
• Physical Design
• Field-Programmable Gate Arrays (Fpga)
• Mixed Signal
• Application-Specific Integrated Circuits (Asic)
• Very-Large-Scale Integration (Vlsi)
• Timing Closure
• Embedded Systems
• Eda
• Cmos
• Integrated Circuits (Ic)
• Analog
• Rtl Design
• Integrated Circuit Design