Jayant Bhasker
- Role
- Senior Dft Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jayant Bhasker
DFT Engineer with around 5 years of experience currently at Analog Devices and worked at…
Experience
Senior Dft Engineer
Jul 2021 — Present · Bengaluru, IN
Implemented and integrated DFT features including JTAG/iJTAG 1149.1/1687), SSN/STF, BSCAN, EDT/OCC, and process monitors at SoC level.# Delivered patterns to ATE and supported pre/post-silicon validation and debug.# Performed static checks – SpyGlass DFT, Lint, CDC, RDC – ensuring 100 % scan-flop and DFT rule compliance.# Hands-on with Siemens Tessent suite and SpyGlass DFT for scan, MBIST, and static verification.# Collaborated cross-functionally across RTL, verification, and test teams to ensure seamless DFT sign-off and silicon readiness.# Executed scan insertion, ATPG coverage debug, and test-point insertion, achieving >99 % stuck-at and >90 % transition fault coverage.
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