Jay Kumar Das
ASIC Design Engineer at AMD | SiFive | ECE | BE
- Role
- Asic Design Engineer (Contractor) at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jay Kumar Das
Physical Design Engineer & CAD-PD & Physical Verification with almost 4.2 years of…
Experience
Asic Design Engineer (Contractor)
Sep 2022 — Present · Bengaluru, IN
AMD offers a great enviroment to work and learn. I Joined the clocks teams and successfully completed 1 tapeout in 4nm technology.Key factors to add in my role- 1. Handeling Two block from MPU level. Did Top layer Clock routing on the clocks nets.2. Making strategies for the planning of TMAC with respect to the length apart from tapping points and also looking by functionality by know the driver load and capacity.3. After manual routing, clean up with LVS.[Open, shorts and floating routes] from Top layer.4. Worked with ChipTile owner to fix issue regarding FM issues, Annotation, Clock tran, Drv.5. Worked on FCPV, to clear Metal DRC, Base DRC, ERC, EDRC.6. Taken the full ownership, in clearing TilePMHotspots from FCPV_containers.
Education
Army Institute of Technology, Pune
Bachelor of Engineering - BE
2017 — 2021
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