Jatin Maranal
Lead Cpu Rtl Design Engineer @Cadence
Austin, TX, US
EMAILS
MOBILE NUMBERS
+91 *********19
Signup · Get unlimited contacts
WORK HISTORY
Dec 2025 — Present
Lead Cpu Rtl Design Engineer @Cadence
View department →
Austin, TX, US
EDUCATION
N/A
National Institute of Technology Karnataka
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
N/A
North Carolina State University
Master of Science - MS, Computer Engineering
ABOUT JATIN MARANAL
Graduate student pursuing Master of Science in Computer Engineering at NC State University, with over 3 years of experience as a Hardware and RTL Design Engineer in Prototype Development role. I have a proven track record in handling high speed data flows and implementing memory-intensive processing algorithms in RTL on FPGA and RFSoC platforms.
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.