Jatin Maranal
Lead CPU RTL Design @ Cadence | MS Computer Engineering @ NCSU | Ex - RTL Design Engineer @ Bharat Electronics Limited
- Role
- Lead Cpu Rtl Design Engineer at Cadence
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Jatin Maranal
Graduate student pursuing Master of Science in Computer Engineering at NC State University, with over 3 years of experience as a Hardware and RTL Design Engineer in Prototype Development role. I have a proven track record in handling high speed data flows and implementing memory-intensive processing algorithms in RTL on FPGA and RFSoC platforms.
Experience
Lead Cpu Rtl Design Engineer
Dec 2025 — Present · Austin, TX, US
Education
National Institute of Technology Karnataka
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
North Carolina State University
Master of Science - MS, Computer Engineering
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