Jaswanth Pamuru
Design Verification Engineer @Chipsolve Technologies Pvt limited ll M Tech Microelectronics & VLSI @NIT CALICUT (2023-2025)
- Role
- Design Verification Engineer at Chipsolve Technologies Private Ltd
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Chipsolve Technologies Private Ltd
Jul 2025 — Present · Hyderabad, IN
Education
Jawaharlal Nehru Technological University, Anantapur
Bachelor of Technology - BTech
2019
National Institute of Technology Calicut
Master's degree
2023 — 2025
National Institute of Technology Calicut
Masters of technology - M.Tech Microelectronics and VLSI Design
2023 — 2025
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.