Jaspreet Singh Saluja

About Jaspreet Singh Saluja

I\'m the engineer who takes complex, high-dependency programs — often with significant ambiguity — and makes them ship.Over 15 years, I\'ve architected verification strategies for some of the most complex silicon shipping today: Microsoft\'s Azure MAIA AI accelerators and five generations of NVIDIA GPUs spanning 20+ chip products. My work has consistently resulted in first-spin A0 silicon success — a track record I\'ve maintained across every program.I specialize in the verification at the crossroads of hardware, firmware, and system-level correctness: secure boot, clock management, hardware root-of-trust, thermal protection, fusing — mission-critical subsystems where a single bug means the chip doesn\'t power on. I\'ve taken these IPs from empty directories to coverage closure, building UVM testbenches from scratch, writing C/C++ firmware co-verification collateral, and then bringing up that same silicon on ATE wafer platforms and validation boards.My true differentiator is what I do with that depth. I map dependencies across ten teams, build trackers, align owners, fill gaps myself when needed, and drive to closure. I\'ve done this across IP verification, SoC-level features, and now multi-die chiplet integration with external vendors. When the path forward is unclear and the stakes are high, I figure it out and deliver.This instinct was pressure-tested when I co-founded an AI startup. I walked in knowing nothing about LLMs or RAG — and within months shipped full-stack AI applications including RAG pipelines and LangGraph agentic workflows. I now apply these skills to pioneer AI-augmented verification, from AI-generated UVM scaffolding to automated spec-to-API translation.I thrive in high-stakes environments where someone needs to cut through complexity, align teams, and ship.

Experience

1. Director - Design Verification

   Microsoft

   Jun 2024 — Present · Mountain View, CA, US

   Verification architect and technical driver for Microsoft\'s Azure MAIA AI accelerator — a next-gen chiplet-based architecture for large-scale AI workloads. Part of the founding DV team from incubation; own a unique charter spanning IP and SoC-level verification, a scope typically held further up the technical ladder.Chiplet Cold Boot & MCM Integration Architect: Single point of ownership for the complete SoC cold boot sequence and chip initialization across a multi-die chiplet architecture. Integrate firmware libraries into the MCM testbench and build the infrastructure enabling all testplan owners to call them seamlessly. Own the validation testplan that qualifies these libraries — a precursor enabling the entire team. Maintain a parallel-forces bringup flow that unblocks owners while firmware is in development. Coordinate delivery across internal teams and a Tier-1 external silicon vendor.Multi-IP Verification at Scale: Own the verification lifecycle for 9+ mission-critical IPs (boot, clock management, root-of-trust, fusing, thermal, data-path control). Built 5 UVM testbenches from scratch; scaled legacy environments for the rest. Absorbed additional IPs and chiplet scope mid-program with minimal headcount increase through rigorous planning.Silicon-Accurate Firmware Qualification: Architect MCM-level testplans that serve as the golden environment for firmware qualification, ensuring simulation fidelity matches real silicon.AI-Augmented Verification Pioneer: Drove AI-assisted workflow adoption across the team — LLM tools for code generation, piloting AI-generated UVM scaffolding on a live IP, and seeding broader AI-driven verification experimentation.First-Spin A0 Track Record: Career-long record of first-spin silicon success across every program — multiple generations of AI accelerators and GPUs, zero respins from verification escapes.

Education

• CodePath

  Android Application Development

  2017 — 2017

• Product School

  Certified Product Manager, Product

• RV College Of Engineering

  BE, Electronics and Communication Engineering

  2004 — 2008

• Doulos

  UVM training, Universal Verification Methodology(UVM)

  2021 — 2021

• North Carolina State University

  MS, Computer Engineering

  2008 — 2010

Skills

• C
• Cdc
• Vlsi
• Simulation
• Vmm
• Jasper
• Perl
• C++
• Android Development
• Application-Specific Integrated Circuits (Asic)
• Processors
• Digital Electronics
• Synopsys Tools
• Logic Design
• Vhdl
• Simulations
• Nc-Verilog
• Rtl Design
• Hardware Design
• Android Stu
• Systemverilog
• Cadence Virtuoso
• Arm
• Vcs
• Perforce
• Soc
• Vi
• Computer Architecture
• Rtl Coding
• Functional Verification
• Linux
• Modelsim
• Asic
• Verilog
• Hardware Architecture
• Windows
• Microprocessors