Jared Reiss-Lavoie
SoC Design Verification Engineer @ Intel
- Role
- Soc Design Verification Engineer at Intel
- Location
- Fort Collins, CO, US
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
About Jared Reiss-Lavoie
I\'m a lifelong learner driven by curiosity and a passion for solving challenging…
Experience
Soc Design Verification Engineer
Oct 2025 — Present
Education
University of Wisconsin-Madison
Bachelor of Science - BS, Electrical Engineering
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