Japesh K.

About Japesh K.

With a robust background in Physical Design at the block level, coupled with experience in Synthesis, Static Timing Analysis (STA), Logic Equivalence Checking (LEC) analysis, I bring a comprehensive skill set to the table. Proficient in utilizing both Synopsys and Cadence toolsets, I have a proven track record of performing synthesis, floorplan and place to route at the block level and adeptly identifying and resolving timing and design-based violations. My expertise extends to working on various complex IO protocols and executing Engineering Change Orders (ECOs) encompassing both functional and timing adjustments. I am well-versed in conducting timing analysis using Primetime and collaborating closely with Sign-off Physical Verification Teams to ensure the integrity and closure of the block. Additionally, my collaborative approach extends to working closely with CAD teams to address flow-based issues. With a strong commitment to effective communication and collaboration, I am adept at working remotely with diverse teams, ensuring project success and alignment across all stakeholders.

Experience

1. Senior Engineer

   美商高通國際股份有限公司

   Apr 2025 — Present · Austin, TX, US

Education

• Punjab State Board of Technical Education and Industrial Training

  Diploma

  2012 — 2015

• CHANDIGARH UNIVERSITY

  Bachelor of Engineering, Engineering

  2015 — 2018