Janeesh Jc

About Janeesh Jc

Experience with Methodology based verification using OVM/UVM and ARM SoC based verification in a C based test setup Experience in customer interaction and demonstration at customer place Experience in System Verilog Experience in conventional verification and FPGA validation Experience in fault simulation and functional safety – ISO26262 Experience in protocols Such as USB2.0, AMBA-AHB, APB, Ethernet, H.264, MPEG2TS Excellent team leading skills, time management skills with proven ability to work accurately and quickly prioritize coordinate and consolidate tasks.

Experience

1. Associate Director

   Samsung Semiconductor

   Sep 2021 — Present · Bengaluru, IN

Education

• Sathyabama University

  M. E, Applied Electronics

  2004 — 2006

• Manonmaniam Sundaranar University

  B.E, ECE

  1999 — 2003

Skills

• Usb
• System Verilog
• System on a Chip (Soc)
• H.264
• Functional Verification
• Verilog
• Altera Quartus
• Vlsi
• Logic Analyzer
• Fpga
• Universal Verification Methodology (Uvm)
• Open Verification Methodology
• Ovm
• Altera
• Static Timing Analysis
• Vhdl
• Modelsim
• Systemverilog
• Amba Ahb