Janardhan Eerappa
Seasoned DFT professional in definining architecture for successful and ontime SoC execution with silicon testing.
- Role
- Director Silicon Design Engineering at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Janardhan Eerappa
Specialties: Design for Test/debug, DfT Flow and methodology, environments setup and usage.DfT Architecture and Strategy definition for ASIC, SoCs, of Mixed Signal designs.DfT technical management of onsite/offshore teams.Test program strategy and definition.Design debug using DfT techniques.Build team, Mentoring and coaching team members to excel in DfT.Project Management, customer interface and people management
Experience
Director Silicon Design Engineering
Nov 2023 — Present · Karnataka, IN
Education
B. M. S. College of Engineering
BE, Electronics and Communication
1994 — 1998
Skills
- Formal Verification
- Logic Bist
- Rtl Coding
- Scripting
- Scan Insertion
- Test Automation
- Dft Verification
- Verilog
- Jtag
- Project Planning
- Logic Synthesis
- Atpg
- Testbench Development
- Technical Resource Management
- Vhdl
- Design for Debug
- Dft Constraints
- Dft Architecture
- Dft Drc Analysis
- Test Validation
- Team Building
- Memory Bist
- Testing
- Boundary Scan
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