James George
Senior Lead Engineer at Qualcomm
- Role
- Senior Lead Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About James George
Experienced Design Verification Engineer with a demonstrated history of working in the VLSI Industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, SVA, Functional and code coverage, Verilog, GLS, Bus Certification, Power Aware simulations, Perl Scripting and Debugging skill and Protocols like Ethernet (100G/50G/25G/10G/5G/2.5G/1G/100M/10M - MII, RMII, RGMII, SGMII, USXGMII, XSBI), PCIe (Gen1/Gen2/Gen3/Gen4), Functional Safety(FuSA), TestChips etc.
Experience
Senior Lead Engineer
Dec 2023 — Present · Bengaluru, IN
Education
TKM College of Engineering , Kollam
B.Tech, Electronics and communication Engineering
2009 — 2013
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
MAVEN SILICON
ADVANCED VLSI RN COURSE, Front end chip design,verilog, system verilog,UVM,Perl
2014 — 2015
Skills
- Uvm
- Matlab
- Verilog
- System Verilog
- Universal Verification Methodology (Uvm)
- Engineering
- Vhdl
- Systemverilog
- Teamwork
- Very-Large-Scale Integration (Vlsi)
- Verilog
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