James Kim
Senior Analog Digital Design Engineer @Microchip Technology Inc.
San Francisco, CA, US
EMAILS
MOBILE NUMBERS
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WORK HISTORY
Aug 2019 — Present
Senior Analog Digital Design Engineer @Microchip Technology Inc.
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San Francisco, CA, US
FPGA Memory block design, SoC Compiler SRAM (Dual/Quad) & Custom circuit design, RTL coding(System Verilog) design(Mento Questa), Low Power design, High Speed(Fanout) design,High Sigma Analysis (Solido), High Sigma calculation, NBTI modeling, High Speed IOG Rx/Tx timing verification(VCD to SPICE)
EDUCATION
N/A
Korea University
Master's Degree
N/A
Korea University
Bachelor’s Degree
SKILLS
VlsiAsicFailure AnalysisMemoryDynamic Random-Access Memory (Dram)SimulationsIntegrated Circuit DesignElectrical EngineeringMixed SignalCircuit DesignAnalogDramSramPhase Change MemoryCmosAnalog Circuit DesignDdrIcSemiconductorsCharacterization
ABOUT JAMES KIM
SoC Special Memory Block design, High Speed Data Path design, RTL coding for all blocks…
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