Jameel Koita

About Jameel Koita

Technical engineering leader with experience building high performance SOC designs across mobile, compute and data center products.Experience managing multiple product families, with expertise in leading and growing teams across multiple countries.Currently leading the physical design effort for several Microsoft silicon products, being deeply involved in product architecture, floorplan definition, cost optimization and vendor management.

Experience

1. Senior Director, Hardware Engineering

   Microsoft

   Jan 2022 — Present · Portland, OR, US

   Driving end-to-end physical design strategy and execution for advanced SoC and IP development. Leading global teams to achieve aggressive power, performance, and area (PPA) targets while accelerating time-to-market for next-generation semiconductor products on advanced technology nodes. Focused on innovation, automation, and operational excellence to reduce cost, improve scalability, and enable business growth.

Education

• University of Washington

  Master of Business Administration - MBA

  2017 — 2019

• University of Mumbai

  B.E., Electronics Engineering

  2002 — 2006

• University of Southern California

  M.S., Electrical Engineering

  2006 — 2008

Skills

• Asic
• Rtl Design
• Cadence Virtuoso
• Vlsi
• Testing
• Electrical Engineering
• Semiconductors
• Perl
• Verilog
• Pcb Design
• System on a Chip (Soc)
• Application-Specific Integrated Circuits (Asic)
• Soc
• Static Timing Analysis
• Very-Large-Scale Integration (Vlsi)
• Physical Design
• Debugging
• C++