J Liang
- Role
- Design Verification Engineer at Meta
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About J Liang
Design Verification leader with extensive hands-on experience in pre-silicon…
Experience
Design Verification Engineer
Oct 2021 — Present
Skills
- Shell Scripting
- Formal Verification
- Embedded Systems
- Bus Certification
- Smmu
- Debugging
- Perl
- Vhdl
- Arm
- C
- Device Drivers
- Processors
- Verilog
- Functional Verification
- Smmu
- Testing
- Uvm
- Eda
- Soc
- Asic
- C++
- Systemverilog
- Fpga
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