Jai S
Logic Design Engineer at Intel Corporation
- Role
- Logic Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jai S
Logic Design Engineer
Experience
Logic Design Engineer
Aug 2017 — Present · Bengaluru, IN
Education
Manjeera Junior College, Warangal
Intermediate, MPC
2009 — 2011
National Institute of Technology Warangal
Master of Technology (M.Tech.), VLSI Systems Design
2015 — 2017
Bishop Beretta High School, Kazipet, Warangal, Telangana
Schooling, High School/Secondary Diplomas and Certificates
2006 — 2009
Kakatiya Institute of Technology & Science, Yerragattu Hillocks, Bheemaram, Hasanparthy, Warangal
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
2011 — 2015
Skills
- Mixed-Signal Ic Design
- Upf (Unified Power Format)
- Design Compiler
- Systemverilog
- Vhdl
- Microsoft Powerpoint
- Tanner
- Perl
- Public Speaking
- Digital Ic Design
- Mbist
- Kave
- Management
- Dft
- Project Management
- Leadership
- C
- Programming
- Tessent Mbist
- Microsoft Word
- Customer Service
- Verilog
- Lintra
- Rtl Design
- Kicad
- Xilinx Vivado and Ise Tools
- Research
- Cadence
- Analog Ic Design
- Pcie
- Microsoft Excel
- Powerpoint
- Digital Circuit Design
- Visa (Virtualization of Internal Signal Architecture)(Dfx)
- Serial Protocols
- Microsoft Office
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