Jairaj Rao

About Jairaj Rao

work experience in the field of ASIC/FPGA,SOC microarchitecture/design/verification/implementation for digital, mixed signal ICs.*Work experience in ASIC flow from RTL to GDSII in multiple technology nodes.*Work experience in Bluetooth, gnss, 4G-LTE/5G,radio protocols.*Signal processing(DSP) and wireless communication experience, mixed signal design experience, HW/SW Partitioning, Low Power designs, HW accelerators.* Perform RTL coding(system verilog, verilog,vhdl),LINT, CDC, system verilog assertions, unit/integration level verification(UVM/OVM),synthesis,timing(STA).

Experience

1. Digital Design Engineer

   Cirrus Logic

   Aug 2019 — Present

   HW based security subsystem (crypto graphic function),NVM or flash controller, mixed signals SoC, Audio codec design, clocking/power architecture, data-procesing IP development

Education

• University at Buffalo Graduate School

  MS, Electrical Engineering

  2009 — 2011

• Visvesvaraya Technological University

  B.E, Electronics and communication

  2002 — 2006

• Mahatma Gandhi Memorial College, Udupi - 576102

  12TH, PCMB

  2000 — 2002

Skills

• Fpga
• Asic
• Hardware Architecture
• Debugging
• Semiconductors
• Wireless Technologies
• Logic Synthesis
• Modelsim
• Tcl
• Signal Processing
• Functional Verification
• Xilinx
• Systemverilog
• Computer Architecture
• Rtl Coding
• Semiconductor Industry
• Integrated Circuit Design
• Digital Signal Processing
• Systems Design
• C
• Vlsi
• Vhdl
• Digital Signal Processors
• Arm
• C++
• Verilog
• Soc
• Cmos
• Integrated Circuits (Ic)
• Wireless
• Logic Design
• Rtl Design
• Embedded Systems
• Eda
• Static Timing Analysis
• Radio Frequency (Rf)